The Air Force Office of Scientific Research (AFOSR) has announced a new basic research initiative seeking to bring together the computational hardware, software, aerospace sciences, physics, and applied mathematics communities “to develop a novel and unique capability to design, optimize, build, and deploy specialized high-performance computing platforms to speed development of Air Force systems.”

According to the AFOSR’s Broad Agency Announcement (BAA) (emphasis added):

The history of high-performance computing, indeed computational modeling in general, has been portrayed as an arms race between ever faster computer hardware, often characterized by the ubiquitous Moore’s law describing the exponential growth in our ability to put computing machinery onto integrated circuits, and the equally advancing capability of complex software and algorithm designers to exhaust the memory and processors of this hardware in pursuit of ever more accurate and speedy simulation technology. In actuality, this process has always been a symbiotic relationship… Now, despite the decades of progress from this paradigm, our ability to develop high-performance chips is starting to slow from Moore’s goals. Additionally, the shear cost of electricity to drive these systems is pushing the community at large to consider new methods to continue the advance of computational science and engineering [more following the link].

 

The effects of both power consumption and the slowing from Moore’s law can already be observed in the computer industry. A bewildering array of new architectures has emerged: A buyer of computer hardware must now choose between various configurations of multi-core central processing units, graphical processing units, multi-threading programming methods, and new computer languages to program these different architectures. Some communities have gone even further with the design of specialty chips that only perform a single algorithm… Between these extremes is the philosophy of “co-design,” where the hardware is commercial equipment, but the topology is tuned to a specific algorithm. This approach has demonstrated three orders of magnitude performance improvement over the same number of chips in a standard configuration for certain applications. The challenge, however, for this emerging field is that much of the effort is currently focused on tuning hardware to existing algorithms in a process that is highly experimental, often using surrogate hardware, such as field-programmable gate arrays, to develop the computational system. Thus, there is a clear need for a fundamental basic research program wherein the hardware and algorithms are placed on an equal footing to develop specialized, heterogeneous, and very high-performance systems to answer the computational objectives of the Air Force and the Department of Defense.

AFOSR’s primary objective with this program therefore is to (emphasis added):

…produce the fundamental research to enable highly focused, potentially heterogeneous, computational platforms that offer orders of magnitude better performance for single application areas. Examples include, but are not limited to, specialized systems for (a) virtual wind tunnels, (b) material performance, degradation, and lifetime studies in the “virtual twin” concept where a model tracks the performance history of an actual component (wing or airframe), and (c) dedicated software systems that link physics software for the design of directed energy weapons with electromagnetic propagation/engagement tools to advance the state-of-the-art in both technology and operational concepts of lasers and high power microwave devices…

 

Thus, this effort will be focused on fundamental and interdisciplinary research in computational hardware, computational software, and mathematical models, and is especially interested in work that characterizes the relationship between hardware and algorithms. In the hardware context, fundamental study of both processing units, such as central processors, graphical processors, dedicated digital signal processing chips (e.g. fast Fourier transforms chips), specialty single purpose chips (e.g. “GRAPE” [for GRAvity PipE] chips) and heterogeneous combinations of the various processing units as well as novel means to design memory architecture for fast and accurate calculations will be necessary. Tools from the hardware community for design and characterization will be important as well. For computational codes and software, scalable algorithms that benefit from specific instantiations in hardware, either due to routines that perform well on specific processing chips or data structures that exploit novel memory configurations, will be supported. Finally, efforts in applied mathematics to jointly model both hardware and software will be supported, as will research on how to optimize the multiple and conflicting requirements between these interdisciplinary systems. Preference will be given to teams that integrate these research threads into a coherent agenda for specialized, high-performance computing architectures for Air Force and Department of Defense applications.

AFOSR suggests submission of proposals by June 1st, with white papers submissions to program managers also encouraged. The total anticipated level of funding is $2.4 million per year for five years for at least two teams.

Ultimately, the program “will create a new community of researchers skilled in the design, development, and deployment of systems tuned to maximize the synergy of advanced algorithms and high-performance hardware.”

For more details, check out the entire BAA. Questions should be directed to the cognizant AFOSR program officers, including Douglas Smith.

(Contributed by Erwin Gianchandani, CCC Director)