The following is a special contribution to this blog by CCC Executive Council Member Mark D. Hill of the University of Wisconsin-Madison.

A key driver behind the amazing progress in computer performance and computer cost-performance has been Moore’s Law (doubling transistors per chip every two years) and Dennard Scaling (doing so at roughly constant power). Many have been warning that there are challenges with both and that new action is need to use transistors more efficiently. See for example the National Academies 2011 report “The Future of Computing Performance: Game Over or Next Level?” and the Computer Community Consortium 2012 white paper “21st Century Computer Architecture”.

Intel has long been a contrarian on these warning, arguing that technology scaling will continue into the foreseeable future. A recent Fossbyte report “Intel Accepts That Moore’s Law Is Finally Dead, Drops Its ‘Tick-Tock’ Model Of Chip Making”, however, claims that even Intel is showing concern. The report claims that Intel plans to alter its long-used “tick-tock” model, wherein annual improvements alternate between architecture and technology scaling. (This model had been used by many companies and was arguably pioneered by IBM, but without the memorable name).

To many, the challenges to technology scaling provides a push to innovate more at other levels. See for example 2015 Computer Community Consortium white paper “Opportunities and Challenges for Next Generation Computing” and the call for an the upcoming “Architecture 2030 Workshop @ ISCA 2016”. More generally, I see these changes also as opportunities to innovate in more radical dimensions, such from security to wearability to greenness.